GPMC logic analysis

After struggling a bit (actually a lot), I manage to extract data from BBB on FPGA, the following graph is the output captured by Quartus II SignalTap2 analyzer. Here I use multiplexed mode in GPMC to conserve GPIOs, this means that address and data are share the same signal path.
The second graph is the timing diagram I copied from AM335X datasheet, address is latched into FPGA on rising edge of ADVN signal, then data is latched or send on falling edge of wen/ oen signal.
At the stage, I have basically connect my BBB to FPGA successfully which means my Linux OS is able to control external device to perform different hardware functions.