UDP connection programming

Although I plan to use BBB as my embedded host, I want to transfer data from BBB to my host PC as well for one major reason; data verification and display. Simply because coding on desktop computer is easier to setup and rich ready to use library can be used to display my data. 

There are many ways to communicate with BBB such as TCP/ UDP, USB, UART, I chose UDP to be my main communication method for its simplicity and speed. UDP libraries are already in GCC, allI have to do is to implement the libraries.  

You just have to put the data pointer, number of bytes to be sent and destination IP address, the data will be sent from BBB to PC. 

size_t udpTXClient(const void *bData, int nSize, char *IP){

struct sockaddr_in serv_addr;

    int sockfd, i, servLen;

size_t nTxLen; 

size_t nWriteLen; 

    if ((sockfd = socket(AF_INET, SOCK_DGRAM, 0))==-1)

        err("socket");

servLen = sizeof(serv_addr);

    bzero(&serv_addr, sizeof(serv_addr));

    serv_addr.sin_family = AF_INET;

serv_addr.sin_addr.s_addr = inet_addr(IP);

    serv_addr.sin_port = htons(1111);

//printf("UDP sender enabled\r\n") ;

if((nTxLen = sendto(sockfd, (void *)bData, nSize, 0, (struct sockaddr *) &serv_addr, servLen))==-1)

printf("UDP TX client fail\r\n");

    close(sockfd);

return nTxLen; 

}

GPMC registers setup

A quick snap of my GPMC registers setup on AM335X, I reconfigure the register values through Kernel Module programming and display the value by using prink. The the signal analyzer diagram from my previous article is the result of this setup.

GPMC logic analysis

After struggling a bit (actually a lot), I manage to extract data from BBB on FPGA, the following graph is the output captured by Quartus II SignalTap2 analyzer. Here I use multiplexed mode in GPMC to conserve GPIOs, this means that address and data are share the same signal path.
The second graph is the timing diagram I copied from AM335X datasheet, address is latched into FPGA on rising edge of ADVN signal, then data is latched or send on falling edge of wen/ oen signal.
At the stage, I have basically connect my BBB to FPGA successfully which means my Linux OS is able to control external device to perform different hardware functions.

Hardware connection

Finally, have my PCB ready and beaglebone black connect to my DE2-115 board. After connecting BBB to DE2-115, both boards can be booted on successfully!! I have checked some basic functions of BBB such as Ethernet, Uart and I2Cs, works fine at the stage.
Now, the challenge is waiting ahead, I have write a GPMC driver to port BBB to DE2-115, a Linux AP program to interface with PC and verilog for FPGA digital logic.